1. Field of the Invention
The present invention relates to a continuous-time delta sigma modulator.
2. Description of the Background Art
A continuous-time delta sigma analog-to-digital converter is known from “A 20-mW 640-MHz CMOS Continuous-Time ΣΔ ADC with 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB,” Mitteregger et al., IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 41, No. 12, December 2006. To eliminate influences on the loop stability, the loop capacitors are trimmed, either statically or in operation. To this end, the appropriate discrete capacitor value must be ascertained. In contrast to a static trimming, only a dynamic trimming of a non-active modulator can eliminate temperature influences on resistors and clock frequency (fclk). A dynamic trimming of an active modulator can briefly result in converter errors.
In DE 10 2008 020 452 A1, which corresponds to U.S. Pat. No. 7,893,518, assembled semiconductor components are produced in an array of identical (semiconductor) elements that are arranged on a wafer distributed about a common focus in order to compensate for possible gradients of inhomogeneities of process parameters (layer thicknesses, doping, etc.) that result from process tolerances along the surface. The individual elements are relatively large in size.